Hard Disks with rotating magnetic platters are being replaced with more reliable Solid-State Drives (SSDs) using semiconductor flash memory. NAND flash memory, invented by Dr. Fujio Masuoka of Toshiba in 1987, uses electrically-erasable programmable read-only memory (EEPROM) cells that store charge on a floating gate. Cells are typically programmed by an avalanche current, and then erased using quantum-mechanical tunneling through a thin oxide. Unfortunately, some electrons may be trapped in the thin oxide during program or erase. These trapped electrons reduce the charge stored in the cell on subsequent program cycles when a constant programming voltage is applied. The programming voltage may need to be raised to compensate for the trapped electrons.
As the density and size of flash memory has increased, the cell size, cell reliability, and lifetime have all been reduced. The number of program-erase cycles that a flash memory is guaranteed to be able to withstand was around 100,000 cycles, which allowed for a lengthy lifetime under normal read-write conditions. However, smaller flash cells have experienced a disturbingly higher wear. Newer flash memories may be spec'ed at less than 10,000 program-erase cycles for two-level cells and about 600 program-erase cycles for Triple-Level Cells (TLC). If current trends continue, future flash memories may only allow for 300 program-erase cycles. Such a low endurance could severely limit the use of flash memory, severely impacting Solid-State-Disk (SSD) applications.
It is likely that the underlying flash technology will have lower endurance in the future. Flash drives may compensate for the lower wear tolerance of the underlying flash memories by a variety of techniques. For example, a DRAM buffer on the flash drive may act as a write back cache, reducing the number of writes to the underlying flash memories when the host repeatedly writes to the same data location.
Since DRAM is volatile, data is lost when power is removed. Various battery, super-capacitor, and Universal-Power-Supply (UPS) systems may be used to keep the DRAM powered up and to provide power to store the DRAM contents to a non-volatile memory. SSD controllers that can make use of the various backup systems that may be present on any given system are desired.
Higher density flash memory devices have become more sophisticated. Low-level flash controllers and SRAM buffers have been integrated with the flash memory. Low-level management functions may be performed on the same silicon substrate or in the same package as the flash memory. Such low-level management functions may include a flash translation layer to cache data in the SRAM buffer, bad block management, error correction, wear-leveling, spare and swap blocks, and garbage collection.
It is desired to have a higher-level SSD controller that works with these sophisticated lower-level flash devices that integrate a low-level flash controller with flash memory. Such low-level controller/flash devices are known as Embedded Multi-Media Card (eMMC), Integrated Solid-State Drive (iSSD), and Universal Flash Storage (UFS) devices.
An endurance-enhancing controller for a standard Solid-State Drive (SSD) or a Super-Endurance flash drive is desired that uses advanced management techniques to reduce the number of writes to flash, hence reducing program-erase cycles on the underlying flash memory. A controller that uses one or more of several possible power backup systems to backup DRAM contents into flash memory is desired. A SSD controller that controls sophisticated controller/flash devices such as eMMC, UFS, or iSSD flash devices is desirable.